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Rajkumar Kadam
1877 Scott Blvd, #116
Santa clara, CA 95050
Residence Ph No : (408) 551 0370

Career Objective:
Career position in the design, analysis, and verification
of ASIC in Networking/Telecom area.

Diploma in VLSI (September 1996 March 1997)
CDAC Institute of Pune.

B.E.  Electronics & Telecommunication (1992 - 1996)
Pune University.

Diploma In Electronics (1989 - 1991)
Bombay Technical Board.


Asic Design: Extensive Verilog/VHDL coding experience, Definition
of product architecture, microarchitecture development, C programming
experience, Hardware/Software Coverification experience.

. Involved in design of NIC-155 ATM
. System controller for Correlator Board
. SRAM controller
. Interface logic for MIPS R4500
. Smart card Interface
. SDRAM Controller
. Verification of Giga Bit Ethernet port controller
. Hardware emulation logic for EDRAM.
. Smart media card controller

System Design:
. Designed 8086 based hardware compliant to ISA
  for customized PID controller along with its peripherals
. 8032 based PLC controller
. 8032 based loudspeaker resonance frequency tester
. System level architecture for Correlator board.
. Involved in defining archictecture for Ethernet ADSL
.  Presently working on Sonet Add/Drop multiplexer FPGA

Platforms: Unix,Windows OS, Sun OS

Programming: Graphics LCD driver development, Online process
monitoring software, firmware for 8032/8088 based product

Languages: Verilog, VHDL, C, Perl, Lex, Yacc, Awk, Sed,Tcl/Tk,
8086/88 8031 8085 assembly language programming

Tools Used:
Simulation : Modelsim, VCS,Hardware/Software Co-Verification
Synthesis  : Synopsys, Synplicity, Leonardo
Timing analysis : Motive
P& R       : Altera MaxplusII, M1
Coverage tools : SureCov

Work Experience:
3 years
Previous Company : CG-CoreEl (India)- From April 97 to May 98.
Present company  : GDA Technologies, Inc

Member Of Technical Staff at GDA Technology Inc, San Jose - From
June 98 till today.

Detailed experience :

Setting up Eaglei Environment for Verification of ARM processor
based design, in cycle accurate mode.

Smart Media Card controller : Compliant to SSFDC standard
Architecture development, RTL coding, verification, fpga

SDRAM controller :
RTL coding of Front end for SDRC controller core.

Design of hardware emulation logic for EDRAM :
Architecture development, RTL Coding, Verification.

Design of MIPS Interface unit: Part of SOC Design
Defined the architecture of MIPS SYSAD interface to integrate it
with the already existing SOC submodules with their proprietary
RTL coding, Contributed in hardware/software co-verification.
Full chip RTL and Gate level simulation.

Design of Smart Card Interface:
Designed an architecture compliant to ISO 7816-3 standards, RTL
Setup of Verification environment for EAGLE, Development of
testcases, Synthesis using DC_Compiler, Timing analysis using
Motive tool.

Design of  Correlator System:
Designed an system level architecture involving DSP TMS320C31,
SDRAM Controller Core, PCI Core, Correlator FPGA's. Designed an
architecture for System controller, coded the system controller,
verified it using Verilog test bench environment. This was
targeted for Altera Flex10K FPGA.

Design of  SRAM_Controller:
Architecture development, RTL Coding, Verification.

Design Engineer in CG_CoreEl (India)
Designed ADSL Interface, Verification of NIC-155 chip,
for functional and synthesis bug fixes.